module rd_datas #(parameter RD_LENTH = 3)(
    input                   clk         ,
    input                   rst_n       ,
    input         [2:0]     key_down    ,
    input         [7:0]     rd_data     ,
    input                   trans_done  ,
    output   reg            rw_flag     ,
    output   reg  [23:0]    rd_data_r   ,
    output   reg            data_vld    ,
    output   reg  [7:0]     wr_data     
);

localparam  LENTH = RD_LENTH + 4;

reg     [23:0]  data_r;

reg		[$clog2(LENTH)-1:0]	cnt_byte	    ;
wire			            add_cnt_byte    ;
wire			            end_cnt_byte    ;
reg                         end_cnt_byte_r0 ;

//---------<rw_flag>------------------------------------------------- 

always @(posedge clk or negedge rst_n)begin 
    if(!rst_n)begin
        rw_flag <= 'd0;
    end 
    else if(key_down[1])begin 
        rw_flag <= 1'b1;
    end 
    else if(end_cnt_byte)begin 
        rw_flag <= 1'b0;
    end 
end

//---------<cnt_byte>------------------------------------------------- 

always @(posedge clk or negedge rst_n)begin 
   if(!rst_n)begin
        cnt_byte <= 'd0;
    end 
    else if(add_cnt_byte)begin 
        if(end_cnt_byte)begin 
            cnt_byte <= 'd0;
        end
        else begin 
            cnt_byte <= cnt_byte + 1'b1;
        end 
    end
end 

assign add_cnt_byte = trans_done && rw_flag;
assign end_cnt_byte = add_cnt_byte && cnt_byte == LENTH-1;

//---------<cnt_addr>------------------------------------------------- 

reg		[23:0]	cnt_addr	   ;
wire			add_cnt_addr;
wire			end_cnt_addr;

always @(posedge clk or negedge rst_n)begin 
   if(!rst_n)begin
        cnt_addr <= 24'h02_00_00;
    end 
    else if(add_cnt_addr)begin 
        if(end_cnt_addr)begin 
            cnt_addr <= 24'h02_00_00;
        end
        else begin 
            cnt_addr <= cnt_addr + RD_LENTH;
        end 
    end
end 

assign add_cnt_addr = end_cnt_byte;
assign end_cnt_addr = add_cnt_addr && cnt_addr == 24'h1FFFFF-1;

//---------<wr_data>------------------------------------------------- 

always @(*)begin 
    case(cnt_byte)
        0   :   wr_data = 8'h03;
        1   :   wr_data = cnt_addr[23:16];
        2   :   wr_data = cnt_addr[15:8];
        3   :   wr_data = cnt_addr[7:0];
        default :  wr_data = 8'h00  ;
    endcase
end

//---------<data_r>------------------------------------------------- 

always @(posedge clk or negedge rst_n)begin 
    if(!rst_n)begin
        data_r <= 'd0;
    end 
    else if(trans_done && cnt_byte >=1'b1)begin 
        data_r <= {data_r[15:0],rd_data};
    end 
end

//---------<end_cnt_byte_r0>-------------------------------------------------

always @(posedge clk or negedge rst_n)begin 
    if(!rst_n)begin
        end_cnt_byte_r0 <= 1'd0;
    end 
    else begin 
        end_cnt_byte_r0 <= end_cnt_byte;
    end 
end

//---------<rd_data_r data_vld>----------------------------------------------

always @(posedge clk or negedge rst_n)begin 
    if(!rst_n)begin
        rd_data_r <= 'd0;
        data_vld <=1'b0;
    end 
    else if(end_cnt_byte_r0)begin 
        rd_data_r <= data_r;
        data_vld <= 1'b1;
    end 
    else begin 
        rd_data_r <= rd_data_r;
        data_vld <= 1'b0;
    end 
end
endmodule